COMP 425 MidTerm Review Notes 1 – 10

The following is my review notes for the first mid term for Comp 425

Including Lecture 1 to 10. First two lectures are introduction to early computers. Not much notes are taken.

Lecture 3 (Single Cycle Professor)

There is a tension between language/compiler/software design and Architect/Hardware Designer . To deal with this, we need an interface, the “Instruction Sets”. The assembly language instructions is good for describing architecture operations.

An instruction Set Architecture (ISA) includes

  • Details of the instruction encoding
  • The set of programmer visible states
    • Contents of programmer accessible registers
    • Behavior of PC
    • Status bits

Time/Program = (Instr/Progam) * (avg number of cycles)/instr * time/cycle

The simplest model of ARM architecture contains three stages

(1) Fetch, (2) Decode, (3) Execute

Two styles of implementations

  • Harvard Style
    • Separates Instruction and Data Memory
  • Princeton (Von Neuman) Style
    • Unified Instruction and Data Memory

Ideal Pipeline

  • Each stage takes the same amount of time
  • All instructions go through all stages of the pipeline
  • There is no sharing of resources between two stages of the pipeline
  • The movement of an instruction through the pipeline is not affected by the instructions in other stages

Lecture 4 (Pipelining Our Processor)

Approaches dealing with issues in pipeline

  • Keep the current architecture and make some adjustments
    • Von Neumann Architecture will have an issue pipelining execute and fetch stage at the same time (sharing of memory). As a result, the fetch must be delayed.
  • Create a new architecture
    • The Harvard Architecture is better with separate instruction and data memory

Lecture 5 (Decode and Execute Pipeline Stages)


  • All operations on data operate on data in a register file and typically change the entire register
  • The only operations that affect memory are load and store
    • Can operate on less than an entire register
  • A few instruction formats with instructions typically being one size (eventually added instructions of different sizes)

Hardware components that implement decode and execution logic

  • Mux
    • select one input from many inputs
  • Demux
    • steer the single input to one of the outputs
  • Decoder
    • The decoder activates one of the outputs
  • ALU
    • Two input, Opselect


We used a Mux to select between Immediate and register in the operands

Lecture 7 (Instruction Encoding)

The select signal  for MUX and DEMUX are both lg2(n) bits wide.

  • ARM Reg-Reg instruction (32 bit)
    • format: [imm/reg bit][opcode][rn][rd]…[rm]
  • ARM Reg-Imm (32 bit)
    • format: [imm/reg bit][opcode][rn][rd]…[Imm]

Lecture 8 (Registers, load, Store, and Branch)

One key property of RISC Computer Architecture is that the only pertains that affect memory are load and store.

Data paths for (1) Load Instruction, LDR (2) Store Instruction have been examined.


For RISC processors, all addresses are byte addresses. All instructions are word aligned (32 bit length). It becomes problematic when we keep fetching continuously. (essentially the program counter is a shared resource between two instructions, violating no sharing of resources principle in the pipeline)

Lecture 9 – 10 (Pipeline Hazards)

 Introducing instruction register to partition RISC data path across the three stage pipeline. There can be three kinds of issues with multiple instructions in the pipeline

  • Structural Hazard
    • Def: An instruction in the pipeline may, at the same time, need a hardware resource being used by another instruction in the pipeline
    • Example: Sharing memory access in Von Neumann model
  • Control Hazard
    • Def: An instruction may determine the next non sequential instruction to be executed
    • Example: branches, interrupts
  • Data Hazard
    • An instruction may produce data later than when it is needed by a following instruction

Dealing with a control hazard in hardware by inserting hop (pipeline bubble). A NOP is really a MUX before instruction register. To deal with data hazard, the hardware could freeze the pipeline until the data from the multiplier is read (interlocks).

Three approaches to resolve Data Hazard in Hardware

  • Freeze the earlier pipeline stages until the data becomes available
  • Bypass the data needed to the right stage
  • Speculation about the resolution to the hazard and undo the effects of the speculation
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